1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming self-aligned device level contact structures on integrated circuit products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region. The gate structures for such transistor devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. In contrast to a planar transistor device, which as the name implies has a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. That is, the gate structure of a FinFET device may be positioned around both the sides and the upper surface of a portion of a fin that was previously defined in the substrate to thereby form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. That is, unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. For a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.
For many early device technology generations, the gate structures of most transistor elements (planar or FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode and a silicon nitride gate cap layer. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. The replacement gate process may be used when forming planar devices or 3D devices. FIGS. 1A-1E simplistically depict one illustrative prior art method for forming an HK/MG replacement gate structure using a replacement gate technique on a planar transistor device. As shown in FIG. 1A, the process includes the formation of a basic transistor structure above a semiconducting substrate 12 in an active area defined by a shallow trench isolation structure 13. At the point of fabrication depicted in FIG. 1A, the device 10 includes a sacrificial gate insulation layer 14, a dummy or sacrificial gate electrode 15, a sidewall spacer 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 12. The various components and structures of the device 10 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 14 may be comprised of silicon dioxide, the sacrificial gate electrode 15 may be comprised of polysilicon or amorphous silicon, the sidewall spacer 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate 12 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 10 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high performance PMOS transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 10 have been formed and a chemical mechanical polishing (CMP) process has been performed to remove any materials above the sacrificial gate electrode 15 (such as a protective gate cap layer (not shown) comprised of silicon nitride) so that at least the sacrificial gate electrode 15 may be removed.
FIG. 1B depicts the device 10 after one or more etching processes were performed to remove the sacrificial gate electrode 15 and the sacrificial gate insulation layer 14 to thereby define a gate cavity 20 where a replacement gate structure will subsequently be formed. Typically, the sacrificial gate insulation layer 14 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 14 may not be removed in all applications.
Next, as shown in FIG. 1C, various layers of material that will constitute a replacement gate structure 30 are formed in the gate cavity 20. Even in cases where the sacrificial gate insulation layer 14 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the substrate 12 within the gate cavity 20. The materials used for the replacement gate structures 30 for NMOS and PMOS devices are typically different. For example, the replacement gate structure 30 for an NMOS device may be comprised of a high-k gate insulation layer 30A, such as hafnium oxide, a first metal layer 30B (e.g., a layer of titanium nitride), a second metal layer 30C—a so-called work function adjusting metal layer for the NMOS device—(e.g., a layer of titanium-aluminum or titanium-aluminum-carbon), a third metal layer 30D (e.g., a layer of titanium nitride) and a bulk metal layer 30E, such as aluminum or tungsten. Of course, other material combinations are possible.
Ultimately, as shown in FIG. 1D, one or more CMP processes are performed to remove excess portions of the gate insulation layer 30A, the first metal layer 30B, the second metal layer 30C, the third metal layer 30D and the bulk metal layer 30E positioned outside of the gate cavity 20 to thereby define the replacement gate structure 30 for an illustrative NMOS device. Typically, the replacement gate structure 30 for a PMOS device does not include as many metal layers as does an NMOS device. For example, the gate structure 30 for a PMOS device may only include the high-k gate insulation layer 30A, a single layer of titanium nitride (the work function adjusting metal for the PMOS device) and the bulk metal layer 30E.
FIG. 1E depicts the device 10 after several process operations were performed. First, one or more etching processes were performed to remove upper portions of the various materials within the gate cavity 20 so as to form a recess within the gate cavity 20. Then, a gate cap layer 31 comprised of silicon nitride was formed in the recess above the recessed gate materials. The gate cap layer 31 may be formed by depositing a layer of gate cap material so as to over-fill the recess formed in the gate cavity 20 and, thereafter, performing a CMP process to remove excess portions of the gate cap material layer positioned above the surface of the layer of insulating material 17. The gate cap layer 31 is formed so as to protect the underlying gate materials during subsequent processing operations.
In the case of a gate-first process, the material(s) of the gate insulation layer are initially formed above the substrate 12, typically by oxidation (silicon dioxide) or by deposition (a high-k insulating material). Thereafter, the material(s) that will constitute the gate electrode structure (e.g., polysilicon or one or more layers of metal) are deposited above the gate insulation layer. Thereafter, the material for the gate cap layer, e.g., silicon nitride, is deposited above the uppermost gate material layer. A patterned layer of photoresist is then formed above the layer of gate cap material and an etching process is performed to pattern the layer of gate cap material. The patterned layer of photoresist is then removed and the gate material(s) are patterned by performing one or more etching processes using the patterned gate cap layer as an etch mask. Thereafter, silicon nitride spacers are formed adjacent the patterned gate electrode structure which, in combination with the gate cap layer, serves to encapsulate and protect the gate electrode.
Over recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the performance of the individual transistor elements but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements (e.g., transistors) formed in the semiconductor material with the metallization layers, an appropriate vertical device level contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of a transistor, and a second end that is connected to a respective metal line in the so-called M1 metallization layer by a conductive via. As device dimensions have decreased, the conductive device level contact elements have to be provided with critical dimensions on the same order of magnitude. The device level contact elements typically represent plugs or lines, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. For this reason, device level contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate structures. That is, after completing the transistor structure, the silicon nitride materials (the spacer 16 and the gate cap layer 31) that surround and encapsulate the gate electrode structures 30 are effectively used as etch masks for selectively removing the silicon dioxide material between adjacent gate structures in order to expose the source/drain regions of the transistors, thereby providing self-aligned trenches or openings which are substantially laterally delineated by the spacer structures 16 on adjacent gate electrode structures 30.
However, the aforementioned process of forming self-aligned contacts can result in an undesirable loss of the materials that protect the conductive gate electrode, i.e., the gate cap layer and/or the sidewall spacer, as will be explained with reference to FIGS. 2A-2B. FIG. 2A schematically illustrates a cross-sectional view of an integrated circuit product 40 at an advanced manufacturing stage. As illustrated, the product 40 comprises a plurality of illustrative and simplistically depicted gate structures 41 that are formed above a substrate 42, such as a silicon substrate. The gate structures 41 are comprised of an illustrative gate insulation layer 43 and an illustrative gate electrode 44 that are formed in a gate cavity 45 using a gate-last or replacement-gate processing technique. An illustrative gate cap layer 46 and a sidewall spacer 48 encapsulate and protect the gate structures 41. The gate cap layer 46 and the sidewall spacer 48 are typically made of silicon nitride. Also depicted in FIG. 2A are a plurality of raised source/drain regions 50 and a layer of insulating material 52, e.g., silicon dioxide.
FIG. 2B depicts the product 40 after a self-aligned contact opening 54 was formed in the layer of insulating material 52 for a self-aligned contact through a patterned etch mask, e.g. photoresist (not shown). Depending upon the pitch of the gate structures 41, the formation of the contact openings 54 may be done with a single etch mask layer or it may be done using two or more different etch masks. Although the contact etch process performed to form the opening 54 is primarily directed at removing the desired portions of the layer of insulating material 52 (e.g., silicon dioxide), portions of the protective gate cap layer 46 (silicon nitride) and the protective sidewall spacers 48 (silicon nitride) also get consumed during the contact etch process, as simplistically depicted in the dashed regions 56. Loss of protective material in the region 56 can lead to exposure of the conductive gate electrode of the gate structure 41 and create an electrical short with the conductive device level contact that will be formed in the contact opening 54. Such an electrical short can render the affected transistors inoperable for their intended purpose.
Given that the cap layer 46 and the spacers 48 are attacked in the contact etch process, the thickness of these protective materials must be sufficient such that, even after the contact etch process is completed, there remains sufficient cap layer material and spacer material to protect the gate structures 41. Accordingly, device manufacturers tend to make the cap layers 46 and spacers 48 “extra thick,” i.e., with an additional thickness that may otherwise not be required but for the consumption of the cap layers 46 and the spacers 48 during the contact etch process. In turn, increasing the thickness of such structures, i.e., increasing the thickness of the gate cap layers 46, causes other problems, such as increasing the aspect ratio of the contact opening 54 due to the increased height, increasing the initial gate height, which makes the gate etching and spacer etching processes more difficult, etc.
What is needed in the art is a novel process flow that addresses and corrects or lessens at least some of the problems identified above. Accordingly, the present disclosure is directed to various methods of forming self-aligned device level contact structures on integrated circuit products that may avoid, or at least reduce, the effects of one or more of the problems identified above.